A conventional semiconductor device includes an SOI substrate having embedded therein n+ regions. One or more capacitors are arranged in wiring levels over the n+ regions with one plate of the capacitor arranged in a wiring level, e.g., Mx, and another plate of the capacitor arranged in another or lower wiring level, e.g., Mx−1. The plates of the capacitor are connected to the n+ regions via, e.g., wires, via stacks, etc.
Interest has been expressed in installing a metal-on-insulator (MIM) capacitor element into silicon-on-insulator (SOI) technology base. The basic MIM as practiced in bulk technology requires tying both ends of the MIM plates to reverse bias junction in the substrate to eliminate potential charging effects which could damage the MIM. In SOI these diffusions are isolated so an alternate protection scheme is required.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.